e149692cc9
subrepo: subdir: "dotfiles/.vim/plugged/ale" merged: "e4b205440" upstream: origin: "https://github.com/dense-analysis/ale.git" branch: "master" commit: "e4b205440" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
60 lines
2.3 KiB
VimL
60 lines
2.3 KiB
VimL
" Author: Masahiro H https://github.com/mshr-h
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" Description: verilator for verilog files
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" Set this option to change Verilator lint options
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if !exists('g:ale_verilog_verilator_options')
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let g:ale_verilog_verilator_options = ''
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endif
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function! ale_linters#verilog#verilator#GetCommand(buffer) abort
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" the path to the current file is systematically added to the search path
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return 'verilator --lint-only -Wall -Wno-DECLFILENAME '
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\ . '-I%s:h '
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\ . ale#Var(a:buffer, 'verilog_verilator_options') .' '
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\ . '%t'
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endfunction
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function! ale_linters#verilog#verilator#Handle(buffer, lines) abort
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" Look for lines like the following.
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"
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" %Error: addr_gen.v:3: syntax error, unexpected IDENTIFIER
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" %Warning-WIDTH: addr_gen.v:26: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS's CONST '20'h0' generates 20 bits.
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" %Warning-UNUSED: test.v:3: Signal is not used: a
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" %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk
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" %Warning-UNUSED: test.v:4: Signal is not used: dout
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" %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
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" Since version 4.032 (04/2020) verilator linter messages also contain the column number,
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" and look like:
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" %Error: /tmp/test.sv:3:1: syntax error, unexpected endmodule, expecting ';'
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"
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" to stay compatible with old versions of the tool, the column number is
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" optional in the researched pattern
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let l:pattern = '^%\(Warning\|Error\)[^:]*:\s*\([^:]\+\):\(\d\+\):\(\d\+\)\?:\? \(.\+\)$'
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let l:output = []
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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let l:item = {
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\ 'lnum': str2nr(l:match[3]),
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\ 'text': l:match[5],
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\ 'type': l:match[1] is# 'Error' ? 'E' : 'W',
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\ 'filename': l:match[2],
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\}
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if !empty(l:match[4])
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let l:item.col = str2nr(l:match[4])
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endif
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call add(l:output, l:item)
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'verilator',
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\ 'output_stream': 'stderr',
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\ 'executable': 'verilator',
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\ 'command': function('ale_linters#verilog#verilator#GetCommand'),
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\ 'callback': 'ale_linters#verilog#verilator#Handle',
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\ 'read_buffer': 0,
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\})
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